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RTL /Firmware / DFT /ASIC Verification / Physical Design / SOC emulation (CA/AZ)

Company: Xoriant Corporation
Location: Phoenix
Posted on: September 15, 2020

Job Description:

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability, or veteran status. Title ndash RTLFirmware DFT ASIC Physical DesignSOC Emulation Duration 12 months (Will get extend) Mode of interview ndash Skype WebEx Zoom Location ndash Phoenix, AZ San Francisco, CA Type ndash Contract ASIC Design Verification-Phoenix, AZ ASIC Design Verification ndash Sr. Staff Engineer - CL 9 CL 10 We are looking for SoC Design Verification Eng. to provide design verification services for multi CPUDSP SoC. Responsibility Testbench dev. - System Verilog UVM and C tests Integrationdev. of C testsAPIs and SW build flow and UVM mailboxes and HWSW communication components and of lower level UVM test benches Test plan dev. Power-Aware testbench dev. and simulations Seamless porting between simulationemulationprototyping platforms Regression set up and debug for RTLGate Level NetlistUPF PA simEmulationProto Coverage collection and closure Working with cross-functional teams (DVArchDesignFW) to identify coverage scope Min. Qualification 1-3 yrs of relevant exp. in RTL Design and Verification area of which 1 yrs of exp. in SoC Design Verification and HWSW verification. Knowledge of System Verilog UVM and vertical testbench integration, of low-level HWSW interaction and debug, of multi CPU and debug arch., exp. with dev. of fully automated flows Preferred Qualification. Exp. with low-level SW debug - disasm, Tarmac, trace, with core sight arc., embedded SW low-level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security. Exp. with coverage merging across simulation and emulation, Power-Aware and Gate Level Netlist in Emulation, with dev. of fully automated flows, with Gate Level Simulations Python Scripting Physical Design Staff Engineer- Phoenix, AZ Physical Design Develop own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floor-plan, place route, static timing analysis, IR Drop, EM, physical verification in advanced technology nodes Resolve design flow issues related to the physical design, identify potential solutions, drive execution Deliver physical design of an end-to-end IP or integration of ASICSoC design Min. Qualifications 1-3 yrs of exp. Staff Engineer ndash CL10 CL9 Bachelor's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. wlow power implementation signoff, power gating, multiple voltage rails, UPFCPF knowledge. Exp. in Block-level Full-chip floor-planning power grid planning, wPython, TCL, or Perl program. , working wEDA tools like DCGenus, ICC2Innovus, Primetime, RedhawkVoltus or Calibre Preferred Qualifications Exp. in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs Knowledge of static timing analysis and concepts, defining timing constraints exceptions, cornersvoltage definitions Exp. in Block-level Full-chip floor-planning, power grid planning Exp. wcustom or regular clock tree synthesis implementation at the block level or top-level, clock power reduction techniques Exp. wPython, TCL or Perl programming SoC Emulation L1 L2 Engineer ndash Bay Area 1-7 years of experience Port ASICIP RTL to Emulation platforms (Preferred ZebuHAPS) Build a model from released RTL. Generate target platform loadable image(s) test and release the image to Firmware and DV teams. Run sanity tests for qualifying release of the image(s) Release the model to the various team including Functional Validation team, Firmware, DV Assist debug of failures providing an instrumented model ( Waveform Dumps, in-circuit debug) and interfacing with stakeholders. Coordinate with Tools team to validate tool and Model release FPGA and Emulator flows and methodologies Experience with Daughtercards, Speed bridges, Virtual Prototyping Hardware emulators, such as ZebuPalladium or HAPSProtium Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration C and C++ good programming skills. Scripting in Python, Tcl, or Perl Hardware Emulation Platforms and tools Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate In the build Simulation acceleration knowledge (DPI and Transactor) In-depth understanding of RTL and Synthesis Logic simulation VCSNCSIM Programmingscripting skills (C, C++, Python) Firmware Development Sr. Staff Engineer - Bay Area RESPONSIBILITIES Embedded firmware architecture and design to orchestrate hardware accelerators End-to-system firmware development to include power-management, boot loaders, scheduling, RTOS andor bare-metal implementations Develop OS custom kernel drivers and APIs for hardware accelerators and peripherals Support all phases of SoC development ndash including early architecture requirements definition for custom silicon, firmware architecture, implementation, simulation, FPGA debug, chip bring up and support systems and software teams on algorithm development on validated systems Provide high quality software development in conjunction with an ability to lead a multifurcation team allocating task to pursue efficient timely execution MINIMUM QUALIFICATIONS B.S. degree in Computer Science or Electrical Engineering and 10 years of experience in firmware development Experience in software design and programming in CC++ for development, debugging, testing and performance analysis Experience in understanding hardware, clock-level issues, bridges, delays, interrupts, clock gating, polling etc. PREFERRED QUALIFICATIONS 5 years of experience in embedded firmware design for low level OS stack possibly for low-power mobile SoC 10 years of programming in CC++ ( Required ) 2 year of Android or other OS development Experience with lab instrumentation like oscilloscope, logicprotocol analyzers for debugging embedded systems at HW level Familiarity with embedded micro-controllers' architecture Hands-on coding experience with peripherals such as UART, SPI, CSI-2, i2c, GPIO, USB Experience in real-time processing for computer vision and user interaction tasks, high-computethroughput systems and using simulation and modeling technique to estimate performance and power Hands-on experience with FPGA and hardware evaluation boards, EDA design tools, andor ISA simulators Experience with Android KernelFramework experience, linux kernel, ARM Platforms, power management, on-device firmware (MCU or DSP), device bring up and bootloaders, User SpaceCore Services, BSP, Networking, Storage, Wireless, Security, Graphics, Audio. Experience with design and implement OS components at all layers of the system, e.g. kernel, synchronization primitives, resource allocators, memory management, security, IO systems, persistence, etc DFT Staff Engineer ndash Phoenix DFT Engineer professionals advise upon, design, develop andor deliver technology solutions that support best practice business changes Work with the Silicon teams to document the DFT specifications and define the requirements Develop and implement DFT architecture and infrastructure Develop and drive execution of enhanced DFX (DFTDesign-For-Debug) methodologies, with increased focus on debug support Work with the DV team to verify DFT implementations Generate structural test vectors, analyze and improve coveragetest timetest cost Work with designers on STA, physical, power and logical issues impacting DFT Work with test engineers to bring up test vectors on silicon work with lab bring-up teams to bring up test vectors in the lab environment Manage schedules and support internal and external cross-functionalcross-organizational engineering efforts Basic Qualifications Minimum of 3 - 10 years of DFT experience Industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time Developing DFT specifications Industry-standard DFT and design tools Debugging ATPGMBIST patterns STA constraints and their interaction with DFT Bachelorrsquos Degree or equivalent work experience (12 years) or an Associatersquos Degree with 6 years of work experience Preferred Qualifications Experience with Synopsys DFT tools (Tetramax, DFT compiler, BSD compiler, Formality, Spyglass) Experience with JTAG and IEEE standards 1149.1 and 1149.6. RTL Lead Engineer - Bay Area RESPONSIBILITIES Contribute to the development of efficient microArchitectures and contribute to ASIC digital microArchitecture, design and verification Understand our in-house IPs needed and how they need to be integrated, connected and verified Drive the top-level microArchitecture definition and develop the necessary RTL Drive the chip-level integration, verification plan development and verification Supervise the RTL-to-GDS flow and assist with synthesis and timing closure Support the test program development, chip validation and chip life until production maturity Work with FPGA engineers to perform early prototyping Support hand-off and integration of blocks into larger SOC environments Assist with Algorithm analysis, verification and improvement Contribute to ASIC digital architecture, design and verification Ability to communicate clearly Minimum Qualifications 7 years of experience as a Digital Design Engineer andor a Chip Lead Experience in RTL coding, synthesis andor SoC Integration Experience in digital design microArchitecture BS Electrical EngineeringComputer Science or equivalent experience Preferred Qualifications System Verilog OVMUVM experience Python (or similar) scripting experience Python-embedded HDL ndash Magma will be a preferred qualification Experience in SoC integration and ASIC architecture Experience in DFTTestability requirement and test program definition Experience using High Speed interfaces like PCIe, USB, MIPI Master degree in EE Experience in AI andor ML algorithm development will be a preferred qualification Any Query please call on 408 550 1287

Keywords: Xoriant Corporation, Phoenix , RTL /Firmware / DFT /ASIC Verification / Physical Design / SOC emulation (CA/AZ), Other , Phoenix, Arizona

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