Analog Validation Engineer (PDK)
Posted on: January 25, 2023
DE PDK Library Validation is looking for an analog engineer to help
the library QA team and develop automation flows to QA Analog
library collaterals. The candidate will have the opportunity to
work with circuit, process and design rule engineers to validate
the libraries with cutting-edge process technologies.The
candidate's responsibilities include (but are not limited to):
- Develop QA tools/flows to automate Analog library collaterals
- Develop Analog test cases to validate the library
- Collaborate with and provide QA feedback to designers and
- Troubleshoot and provide technical support to users as
needed.Candidate must exhibit communication skills (both oral and
written).This is an entry-level position and compensation will be
given accordingly. #DesignEnablement
You must possess the below minimum qualifications to be initially
considered for this position.Preferred qualifications are in
addition to the requirements and are considered a plus factor in
identifying top candidates.Knowledge and/or experience listed below
would be obtained through a combination of your school work and/or
classes and/or research and/or relevant previous job and/or
Candidate must possess an MS degree with 6+ months of experience in
Electrical Engineering, Computer Engineering, or a related
discipline.Must have the required degree or expect the required
degree by the start date.6+ months of experience in the following:
- UNIX/Linux computing platform.
- Analog/SRAM/VLSI design and physical verification flows such as
LVS, and DRC.
- CAD tools like Cadence Virtuoso or Synopsys Custom Designer,
Cadence Spectre or Synopsys Hspice, Synopsys Star-RC and Synopsys
IC Validator or Mentor Calibre.
Preferred Qualifications1+ years of experience in the following:
- Foundry experience and expertise in developing PDK.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make
every facet of semiconductor manufacturing state-of-the-art -- from
semiconductor process development and manufacturing, through yield
improvement to packaging, final test and optimization, and world
class Supply Chain and facilities support. - Employees in the
-Technology Development and Manufacturing Group -are part of a
worldwide network of design, development, manufacturing, and
assembly/test facilities, all focused on utilizing the power of
Moore's Law to bring smart, connected devices to every person on
Intel strongly encourages employees to be vaccinated against
COVID-19. Intel aligns to federal, state, and local laws and as a
contractor to the U.S. Government is subject to government mandates
that may be issued. Intel policies for COVID-19 including guidance
about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment
without regard to race, color, religion, religious creed, sex,
national origin, ancestry, age, physical or mental disability,
medical condition, genetic information, military and veteran
status, marital status, pregnancy, gender, gender expression,
gender identity, sexual orientation, or any other characteristic
protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in
the industry. It consists of competitive pay, stock, bonuses, as
well as, benefit programs which include health, retirement, and
vacation. Find more information about all of our Amazing Benefits
This role will be eligible for our hybrid work model which allows
employees to split their time between working on-site at their
assigned Intel site and off-site. In certain circumstances the work
model may change to accommodate business needs.
Keywords: INTEL, Phoenix , Analog Validation Engineer (PDK), Engineering , Surprise, Arizona
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